Abstract
In this thesis, we propose a cell delay model for accurately calculating cell delay and peak supply current in the presence of process variations. In addition to cell delay and peak supply current, the output voltage waveform for multiple-input switching (MIS) and non-ramped input can be also derived with our model. Our cell delay model is a current source model (CSM) and is designed to be more complex than traditional CSM for handling the MIS problem and for enhancing the sensitivity to process variations. The complexity and accuracy of our model lay midway between the conventional current source model and the SPICE model. The conventional current source model is accurate and can be fed in non-ramped input. However, it is less sensitive to variations, especially to the individual variations of the transistors in logic cell. Although SPICE model can solve the process variation issue, but the simulation time of SPICE model is too slow compared to that of CSM. Our cell delay model is proposed for solving the issues above. The cell delay errors of our cell delay model are lower than 5% in the presence of variations while the errors are lower than 3% in the cases without process variations. The average cell delay errors are even lower than 0.5% in the presence of process variations. However, the model that we propose is less complex than the SPICE model. Besides, our cell delay model is also capable to deal with the non-ramped input and multiple-input switching cases, as other CSM models can do.