Abstract
In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessary in order to ensure an adequate operating margin for accommodating all kinds of variations (e.g., PVT variation) and to guide the dynamic VDD tuning process as well. In general, a speed grading method for a logic core can be performed by repeating a specific delay test session (e.g., built-in self-test with the latch-off capture scheme), with varying test clock frequencies to derive the maximum operating speed of a specific core under test. In this thesis, we propose an easy-to-use speed grading method featuring a wide-range synthesizable clock generation scheme so that it can support a logic core that could be used with different supply voltages and speeds in different application domains. The clock generation scheme mainly uses the fully synthesizable cell-based phase-locked loop (PLL), the counter-based frequency divider, and the frequency doubling circuit. The generated wide-range clock signal can span from 50MHz to 2GHz under 90nm technology. Since the circuit is fully cell-based, it is easy to do process migration.