Abstract
Minimizing power consumption is one of the key design objectives in today’s integrated circuit (IC) designs. Flip-Flops are important elements in integrated circuit which have a large impact on circuit speed and power consumption. It has been shown [3] that 30% to 60% of the total power is consumed by the clock system, that includes clock distribution network and flip-flops. A double edge triggered flip-flop can latch data on both positive and negative edges of the clock signal, thus, the clock frequency can be halved and significantly reducing the clock network power consumption. In this thesis, we develop a dynamic double edge triggered flip-flop. In contrast to recently published double edge triggered flip-flops [3-10], which need to have pulse signals generated for each clock edges, our flip-flop utilizes clock signal as it is and thus consumes less power. Asynchronous set and reset functions can be easily added to this flip-flop. In addition, scan function can also be added with two approaches. Using TSMC 65LP technology, we demonstrate that the double edge triggered flip-flop can save 48% of clock power as compared to the positive triggered transmission gate flip-flop; while it saves 60% of clock power compared to the dual edge triggered flip-flop [9,14] which employs a pulse generator to enable double edge trigger capability.