Abstract
In modern VLSI designs, the thermal problem is more and more important. Unsmooth distributed temperature will affect upon the reliability of circuits and become the performance bottleneck. Placing cells on appropriate positions can help to obtain desired power dissipation. Once the desired power dissipation is determined, it can be used to calculate the corresponding temperature. As a result, the thermal problem is an important issue that needs to be considered in the placement stage. In this thesis, we study the problem of global placement for standard cells such that the maximum thermal gradient over a chip is minimized. To achieve this objective, we adopt the compact substrate thermal model to compute the thermal profile, and the force-directed method to determine the rough locations of cells. We use the thermal profile to form the additional force, and refine the locations of cells repeatedly until convergence. Different from pervious works, we adopt a simplified transform matrix to get the target additional force. At last, a post processing technique is used to get an even better thermal placement result. Experimental results show that as compared to a given placement without thermal consideration, the thermal gradient can be improved up to 66.7% after running our force-directed approach and post-processing technique, while the wirelength increase is up to 8.81%.