Abstract
In this thesis, we propose a high-throughput low-density parity-check (LDPC) decoder architecture, which is compatible with mobile WiMAX system. Based on vertical shuffled scheduling, we proposed a scheduling method to arrange decoding sequence. The architecture is verified by FPGA system board. Moreover, 90nm technology is used to implement the physical layout. Under 6 decoding iterations, the decoder can achieve highest 746Mb/s, and the power consumption is 90mW.