Abstract
Abstract Electrostatic Discharge (ESD) has always been one of the most important reliability issues for an integrated circuit (IC) design. The principle of ESD is to use a ESD protection circuit to bypass excess electrostatic charges that come in contact with the IC pins and thus protecting the internal core circuit from damages. The important design parameters for an ESD protection circuit is the current sinking capability and the triggering voltage. Below the triggering voltage, the ESD circuit should be off and consumes no standby power. Once the pin voltage is higher than the triggering voltage, the ESD circuit is turned on to sink as much current as possible. In today’s System-on-Chip (SOC) design scenario, multiple voltage supplies are common on a single chip. Thus, it can be expected to have multiple ESD protection circuits to protect different power domains. In today’s design practice, each ESD protection circuit is designed for a specific triggering voltage. Thus, in case of protecting multiple power domains multiple ESD circuits may need to be developed. In this thesis, we propose a method that allows ESD protection circuits with different triggering voltage to be implemented with ease. This method adds stacked diodes (diode string) to a popular ESD protection device GGNMOS, grounded-gate NMOS transistor, to form the individual ESD protection circuit. By changing the number of diodes in the diode string, the triggering voltage can be adjusted. Thus, it enables fast and efficient development of ESD protection circuit with various triggering voltages. Using diode stings for ESD protection is known to have the issue of Darlington Effect, in which leakage current increases the voltage of the shared substrate that lowers the voltage drop across the diode string. This issue needs to be overcome in order to increase the triggering voltage of our ESD circuit. Our approach is to use the triple well to isolate the diode string and the GGNMOS. Putting GGNMOS in a triple well has not been studied before, thus, a thorough study is performed. We show that with proper device structures, it is possible to minimize the extra parasitic vertical bipolar transistor introduced by the triple wells. Thus, the additional voltage drop across the diode string can be fully exerted. One more issue is shown to impact the final triggering voltage, that is, the GGNMOS connection. The GGNMOS has the gate terminal grounded to minimize the standby current before triggering. If the GGNMOS is stacked on top of the diode string, the VGB can then be negative after triggering. This decreases the turn-on efficiency and reduces the effectiveness of our stacked ESD protection circuit. We show that with GGNMOS biased at zero VGB and VGS, no degradation in ESD triggering voltage is observed. In this study, extensive device simulations are performed to verify our theories. Using simulations, we successfully demonstrated that the ESD triggering voltage can be increased by a fixed amount each time a diode is added to the string. Thus, multiple ESD protection circuits with predictable triggering voltage can be developed with ease. This methodology should facilitate future ESD protection circuit design for SOC era.