Abstract
Small delay defects, often escaping from traditional delay testing, could cause a device to function abnormally in the field. Therefore detecting these defects is often necessary in modern delay testing. To address this issue, we propose three test modes in a new methodology called AC+ scan, meaning that the resolution of traditional AC scan test can be enhanced by embedding an All-Digital Phase-Locked Loop (ADPLL) into a circuit under test (CUT). AC+ scan can be executed by a next-generation test platform, HOY platform. The first test mode of our AC+ scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that this method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips will be more likely to cause failure in the field. The third test mode is to extract the waveform of each flip-flop’s output in a real chip. This is made possible by taking advantage of the almost unlimited test memory on HOY test platform, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debug. We have successfully manufactured a Viterbi decoder chip with feature of AC+ scan inside to demonstrate its capability.