Abstract
Technology mapping is a critical step in the FPGA design flow that a ects performance, power consumption, and routability. Moderm FPGAs like Altera’s Stratix series has adopted the adaptive logic module (ALM) structure due to its potential performance and area advantages[1]. An ALM can implement a single logic function or fractured into two smaller LUTs. In this work, we first prove that technology mapping for ALM minimization is a NP-Hard problem. Then we propose an ALM mapping algorithm, ALMmap, for area minimization with bounded depth. We revamp the traditional iterative cut-based mapping flow and introduce a procedure for bounded depth mapping generation with dynamic area recovery that e ectively combines cut selection, mapping and area recovery together. In addition, we introduce a new procedure for cut set determination for ALM minimization under depth constraint. The notion of area flow which has been used successfully for cut selection to reduce LUT count is revised for cut selection to reduce ALM count. ALMmap obtains depth optimal solutions that are 28.3% and 14.1%smaller on average than those produced by a classical mapper[2] and WireMap[3], respectively. The new procedure for bounded depth mapping generation with dynamic area recovery is also effective for traditional LUT mapping and led to 5.5% LUT reduction in traditional 6-LUT mapping compared to WireMap.