Abstract
With the vast advances in chip manufacturing, it is now common to pack many processor cores onto a single chip. Efficient architectural designs of such multicore systems often rely on execution-driven, full-system simulators, such as Gem5. However, as the complexity of the system architectures rises, exploiting the design space is becoming very time-consuming. On the other hand, if the architectural design focuses on specific system components, such as Network-on-Chip (NoC) or memory hierarchy, trace-driven simulations offer an alterna-tive for fast design space exploitation. To enhance the fidelity of traditional trace-based simulators, recent works advocate the use of dependences between trace events to allow the responses of the target component be accounted for in calculating the simulated time. In this thesis, we apply the idea to the NoC simulator of Gem5, Garnet, and discuss how to make Garnet dependency-aware. It turns out that this effort is quite involved and many is-sues have to be resolved. We discuss these issues and show our considerations and solutions. The resultant dependency-aware trace-driven NoC simulator is evaluated by comparing its performance outputs against those from Gem5. Based on our evaluations, the dependency-aware Garnet can keep the performance differences within 3.22%, while the original Garnet may result in errors as high as 14.97%