Abstract
Silicon foundries have had sufficient experiences and reliable results in silicon wafer measurements of nanometer interconnect capacitances and nanometer interconnect resistances. Technology has advanced from 180um, 130um, then into 90nm, with material migration from aluminum to copper as well. In addition to technology evolution, SoC and high-frequency design have been introduced for these years. Due to all the above plus more than eight metal layers and millions of interconnects in each system-on-chip (SoC), we have greater parasitic resistance, greater parasitic, more unpredictable inductance than before. As result, parasitics on interconnect becomes the first factor in performance of a chip. Further, parasitic capacitance highly affects performance either in high-frequency or in low-frequency chip. So, how to model parasitic capacitance efficiently and accurately is an issue now. In the paper, there will be introduction to Raphael, then two simple examples for tutorial, and applications in x-architecture and dummy metal fills at last. And it will give advices and hints how to correlate parasitic capacitance accurately with silicon measurement to help SoC designs.