Abstract
Reliability concerns of a chip are worsening due to the downscaling technology. Among the reliability issues, aging effect is the dominant concern since it degrades the circuit performance over time. Traditionally, run-time monitoring approaches are proposed to estimate aging effects. However, such techniques tend to predict and monitor delay degradation status for circuit mitigation measures rather than the chip health condition. In this paper, we propose an aging-aware chip health prediction methodology which adapts to PVT (Process, supply Voltage, and Temperature) variations and workload conditions. Our prediction methodology adopts an innovative on-chip delay monitoring strategy by tracing representative aging-aware delay behavior. The delay behavior is then fed into a machine learning engine to predict the age of a tested chip. Experimental results show that our strategy can obtain 97.12% accuracy with 4.62% area overhead on average compared with Monte Carlo simulation. To the best of the authors’ knowledge, this is the first work that accurately predicts current chip age and provides future chip health information.