Abstract
This thesis proposed an 11-bit power-efficient 2 bits per cycle (2b/C) successive approximation register (SAR) analog-to-digital converter (ADC) with calibration for wireless communication systems. To achieve a higher operation speed, a 2b/cycle topology is adopted in this work. The Multi-bit per cycle ADC requires multiple comparators and reference voltage to perform the technique. To realize the 2b/C method, an additional digital-to-analog converter (DAC) is needed to generate a reference voltage. The mismatch between the reference DAC and signal DAC will degrade the linearity. The solution is to add redundancy bits to tolerate the error during the AD conversion. Since the comparator offsets will cause linearity error and degradation of ADC performance, an offset calibration is used to cancel the offsets and keep an acceptable linearity. Besides, a 2-step DAC configuration is proposed to reach a lower power and area. Combine the 2b/C DAC and 1b/C DAC, the resolution of reference DAC can be reduced. Hence, the DAC power and area are decreased. This prototype was fabricated by TSMC 90nm 1P9M CMOS technology and the core area is 160x550um2. At a 0.9V supply and a 10MS/s sampling rate with a input frequency of 10kHz, the ADC achieves a SNDR of 55.4dB and a corresponding ENOB of 8.9b. The power consumption is 108 W and it achieves a FoM of 22.6 fJ/conv-step.