Abstract
In our livelihood, Static Random Access Memory (SRAM) appears in the almost electronics and it is required much more area than other circuits in the SoC chip. It shows the SRAM used the most power of a chip. So, how to solve the power consumption issue of SRAM and not to reduce the operating performance of SRAM is a big challenge. To make the power consumption reduce for SRAM, lower operating voltage is an useful method. But SRAM operated at low VDD suffers the following: (1) read disturb and half-select disturb (2) write ability and half-select tolerance trade off, and (3) reduced sensing margin (SM) as well as read failure and slow speeds. Previous works achieved read-disturb-free operations; but do not solve the trade-off between the half-select tolerance and write ability without time-consuming and power-consuming write-back (WB) scheme. All of this issue makes previous work can’t operate at ultra low voltage with higher speed. In this work, we proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read word-line (NRWL) schemes. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-static noise margins (SNM) and the write margin (WM) thanks to the dual data-aware controls of: (1) cell-VSS (DA-CVSS) and (2) write word-line (DA-WWL). NRWL expands the RBL voltage swing and improve the read speed. A fabricated 65nm CMOS logic process 128-row 16Kb D2AW8T SRAM achieved 7.3MHz/48MHz at VDD=210mV/300mV by oscilloscope and Personal Kalos 2 testing. The figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)] is 14+x higher than that of other low-VDDmin SRAM cells.