Abstract
Flash memory is one of the most widely used cores in current consumer products. Given the high demand of mass storage,multi-level cell (MLC) flash has become a cost-effective solution to increase the storage capacity. However, due to limited program/erase cycles of flash, how to maintain the reliability over time is an important issue. Nowadays, error correction coding (ECC) is widely used to enhance flash memory endurance and reliability. Different error correction schemes may lead to different efficiency of redundant memories that store parity bits, and thus different endurance and reliability for a specific flash memory. In this work, we focus on the Bose-Chaudhuri-Hocquenghem (BCH) codes for flash memory, and propose an adaptive-rate error correction scheme that is implemented on the memory controller. Several modes of BCH codes are designed to give different correction capabilities, which require different lengths of parity bits. To store the "extra" parity bits when the originally designed redundant memory capability is not enough for the parity bits, a storage strategy that stores the parity bits in the main memory array is needed. Besides, a configurable linear feedback shift register (LFSR) is shown here to reduce the area of BCH encoder, in which correction capability is changeable. With this error correction scheme, flash memory can trade user storage space for higher error correction capability to keep it usable even when the initially designed ECC can no longer cover the errors.