Abstract
Nowadays the complexity for system chip design is rapidly increasing. In order to reduce the design period, ESL model can be the solution for evaluating during the early system construction. For full system, memory system plays an important role, and it is often considered to be a bottleneck, even affect the performance. Because memory has great influence not only in the performance, but also in the power. We need to develop an ESL memory system model for evaluating the system. For the existing memory system design(DRAMSim2) which is a pure C++ model, the timing it calculates is not accurate. DRAMSim2 only supports one port scheduling policy, but multi-ports memory system design seems to be the mainstream. In our memory model, we support multi-ports memory system design, and some commercial command reordering policies. After verification with RTL memory system, our ESL memory model’s timing accuracy is up to 95%. Its simulation speed is up to 700k cycle/s. For memory system power, we also support power modeling. We divide memory system power into three parts. They are memory controller power, PHY layer power, memory device power. Each power consumption can be estimated individually, and total power consumption is calculated. According to the simplified memory finite state machine, we can estimate most of power consumption. The simulation result shows the power is very close with data sheet. For memory controller power and PHY power, we can obtain its value from cooperation company. These information can be used for evaluating and analyzing the full system design. The result shows the performance will be 10% better after optimized memory controller parameters. We can also do the architecture exploration. After analysis, we obtain 10% better after exploration. On the other hand, we can discuss the trade-off between performance and buffer area to find a balance.