Abstract
Timing analysis has always been an important issue in circuit design. With more variability in integrated circuits, timing analysis must consider the variability in manufacturing or environmental factors, such as temperature and supply voltage. These variabilities make timing analysis more difficult, which directly affect circuit functional correctness and speed. The statistical timing analysis (SSTA) is one approach with fast and accurate results. In SSTA, convergent paths cause difficulty in keeping canonical delay model. In order to capture the expression after sum and maximum operations, we improve the tightness method. In this thesis, a high quality SSTA engine is proposed. This work outperforms the contestants in TAU 2013 variation aware timing analysis contest.