Abstract
Power consumption has become one of the primary challenges in meeting Moore's law. However, the Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption during operation. An automated mapping approach for the SET architecture has been proposed recently for facilitating design realization. In this paper, we propose an efficient enhanced mapping approach consisting of variable reordering, product term reordering, and mapping constraint relaxation techniques to minimizing the area of mapped SET arrays. The experimental results show that our enhanced approach obtains a speedup of 299 times on the mapping time and saves 81\% hexagon count in the mapped SET array compared to the state-of-the-art approach for a set of MCNC and IWLS 2005 benchmarks. Additionally, the experimental results demonstrate the effectiveness of our approach compared with a brute force approach for some affordable benchmarks.