Abstract
We propose an efficient hardware architecture for Inverse Quantization/Inverse Discrete Cosine Transform (IQ/IDCT) in H.264/AVC. Our design supports bypass mode for skipping blocks with zero transformed coefficients. We integrate Run Level Decoding (RLD) into our IQ/IDCT to reduce memory bandwidth. We have integrated the hardware IQ/IDCT into an H.264/AVC main profile decoder in FPGA prototype.