Abstract
Abstract In high-performance system, it is difficult to speed up combinational circuits simply by reducing their critical path delays. Therefore, for the optimization of circuit performance, most IC designers and CAD tools put substantial efforts in minimizing the delay of critical paths. However, critical paths may be rarely activated. This thesis proposes a performance optimization paradigm called Tele-Microscopic Logic (TML) for increasing the throughput based on critical path rarely activated digital systems. The basic idea consists of transforming fixed latency units into variable latency ones that run with a faster clock cycle. This mechanism can improve the average throughput of speed critical designs automatically. In this thesis, we provide an accurate timing analysis and precise critical path activation logic. According to the experimental results, obtained a large set of MCNC benchmarks, the average throughput improvement result is better 43.97% than the circuits without our approach.