Abstract
We propose a hardware implementation including coefficient scanning, inverse quantization and inverse discrete cosine transform for HEVC main profile in this thesis. The design supports 4x4, 8x8 and 16x16 sized transform blocks. It includes a scanning unit, a two-stage pipelined architecture for inverse quantization, a reusable architecture for inverse discrete cosine transform and corresponding control units. The proposed design can support real time decoding of 3840 x 2160 video at 60 fps.