Abstract
We propose a pure hardware implementation of inverse quantization and inverse discrete cosine transform for H.264/AVC high profile video decoding. The proposed design supports 4x4 transform, 2x2/4x4 hadamard transform and 8x8 transform. It includes a run level decoder, a two-stage pipelined architecture for inverse quantization, and a two-stage pipelined architecture for inverse discrete cosine transform. The proposed design is both area-efficient (31K gates) and high performance (100MHz @ TSMC .13 μm). It can support real-time decoding of 3840 x 2160 video @ 30 fps. The design has not only passed gate level simulation but also integrated into a multimedia SoC platform.