Abstract
During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. One efficient way to control the surge current is to schedule the turn-on sequences of sleep transistors. In this paper, we introduce several important properties of the surge current during the power mode transition for the Distributed Sleep Transistor Network (DSTN) designs, which is a popular power gating design style. Based on these properties, we propose an accurate estimation of surge current and provide an efficient schedule on the DSTN structure. Our experiment achieved significantly better results than previous works—on average, 366 times wake-up time reduction and 39.76% less energy loss during the power mode transition.