Abstract
In this thesis, two solutions of brain machine interfaces (BMI) are proposed. Both of them are integrated with analog front-end circuits, stimulation circuits and wireless data transmission module. Moreover, these systems are further combined with the graphical user interface (GUI) to achieve the goal that a complete microsystem can be actually applied in clinical experiments. In addition, this microsystem also provides another treatment with medical efficacy for those patients with Parkinson’s disease. In the version I, a programmable digital core based on modified 8051 is operated at 2MHz clock rate and 1V operation voltage to reduce the power consumption. This digital core provides 8 channels real-time recording as well as 8 channels effective stimulation for acquiring information on how stimulation modulate neural activities and depressing the symptom of Parkinson’s disease. As the recording data from neurons, the Lemp-Ziv lossless data compression circuit compresses the data by the dictionary constructed of input data processing. Additionally, physicians can input the stimulation parameters and observe the recording neural informations on a PC through the graphical user interface (GUI). The digital core integrated with implantable neural microsystem has been fabricated with TSMC standard 0.18m CMOS technology. The power consumption of the digital core is 385W with 2.09*0.59mm2 core area, and the full chip area is 3.06*2.53mm2. In the version II, the prototyping system is proposed for experimental study of the deep brain stimulation (DBS) mechanism by embedding the biomedical signal processing algorithms to biomedical processor. The biomedical processor based on OpenRISC 1200 (OR1200) is implemented to achieve the goal that performs neuron recording with high sampling rate (4KHz) for the purpose of multi-channel recording (2 channels). Therefore, the signal preprocessing, varied resolutions of power spectral analysis(1024, 512 and 256 points) and the ii phase analysis are conducted by this biomedical processor. As this biomedical processor is synthesized by TSMC standard 0.18m CMOS technology, the overall hardware area is 52.8K gate counts and the operating clock rate can be operated at 100MHz. However, the maximum system clock rate is 50MHz in this biomedical platform due to the limitation of the Altera DE2-115 Cyclone IV E EP4CE115F29C7 FPGA board. The resource of this FPGA design costs 3,811 logic elements and 662,528 memory bits. After the electrical measurements for evaluating of these systems, all of the experimental results are presented and discussed in this thesis.