Abstract
For computer system design, accurate modeling and fast simulation of external memories (DRAMs) are key to achieve high performance and efficiency. To adapt the simulation of DRAMs in Electronic System Level design, we study and wrap an existing simulator (DRAMSim2) in the SystemC/OCP environments. Though DRAMSim2 support sophisticated mechanism of DRAM controllers, the simulation works to handle all activities in a cycle-based behavior. Therefore, the idle cycles and activities with long cycles may not be handled efficiently. In this thesis, we proposed an event-based DRAM simulation scheme to address this issue (or more precisely based on SystemC process and events). To verify the proposed ESL model, we constructed test benches based on memory traces (extracted from SPEC CPU2006). For all test benches, the simulated cycles are identical for both simulators and the event-based model is about 1.8x to 14x faster than DRAMSim2-based model.