Abstract
ESL platforms have been built to overcome the design challenges posed by RTL including complex design entries and long verification process, especially for large many-core architectures. However, accuracy of ESL simulation may limit the application of raising to a higher abstraction level. In this thesis, we demonstrate that it's possible to create a fast and accurate ESL platform. First, we start from a parallel software for 3D graphics rasterization on a 44-mesh architecture (with an RTL definition). By profiling the software on an ESL platform based on instruction-level accuracy (hence no timing), we partition the part with a high-instruction count and implement it with a high-level synthesis flow. After verifying the HLS hardware on RTL, we try to augment the ESL platform for all components with correct timings (end-to-end software cycle errors are less than 5\% as compared with RTL). Finally, we are able to run a fast simulation (up to 10x10 mesh with hardware accelerators) to show the overall performance for different configuration of hardware on the ESL platform.