Abstract
SiC has attracted significant attention for power semiconductor devices because of their superior physical and electrical properties: for instance, wide energy bandgap, large critical electric field, high electron saturation velocity, and high thermal conduc-tivity. However, thermal oxidation of SiC needs high temperature (>1100℃) and de-grades the interface property severely. In this thesis, we confirm the effect of phosphorous passivation for the SiO2/4H–SiC interface employing POCl3 annealing. Furthermore, we try to deposit and oxidize Si with a low temperature (700℃ or 800℃) to grow gate dielectric. This way, minimal oxidation of SiC substrate can be anticipated. The POCl3 annealing technique is then applied to the SiO2. A gate dielectric stack structure with Al2O3 on top of the SiO2 is further studied. In the process of depositing Si and low temperature dry oxidation followed by POCl3 annealing (Si+LTO+POCl3), the Dit is reduced to approximately 1×1011 (eV-1cm-2 ) at Ec-E=0.2eV similar to the process of high temperature dry oxidation followed by POCl3 annealing (HTO+POCl3). The μFE of MOSFET using Si + LTO + POCl3 process is higher than 90 (cm2/V-s), but the low yield rate and large leakage current are the major problems. The Si+LTO+POCl3 +Al2O3 gate dielectric stack im-proves the leakage current, and the yield is improved, although the Dit is slightly in-creased to 4×1011 (eV-1cm-2 ) at Ec-E=0.2eV, and the μFE can be retained approxi-mately 60-70 (cm2/V-s) . The HTO + POCl3 technique has a reliability problem reported from the literature. In this study, a gate voltage corresponding to 3MV/cm is applied to stress and com-pare each gate dielectric process. The Si+LTO+POCl3 +Al2O3 gate dielectric process has the least Vth shift. It is attributed to the thinner thickness of phosphorus-doped SiO2 and the Al2O3 on top of it. One of the possible explanations is that the fixed neg-ative oxide charges in Al2O3 hinder electron injection.