Abstract
This Thesis presents a readout integrated circuit (ROIC) with inverter-based capacitive transimpedance amplifier (CTIA), in-pixel correlated double sampling (CDS) mechanism, and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor, executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. CDS is a useful signal processing method to suppress the low frequency noise and fixed pattern noise (FPN). Compared to the conventional CDS, this in-pixel CDS is achieved by only one capacitor and a single switch connected to external reference voltage. Pseudo-multiple sampling technique is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples A prototype 55×65 pixel imager employed these schemes has been designed and fabricated in 0.18μm CMOS technology. The functions and performance of the proposed readout circuit have been verified by experimental measurements at 3.3V supply voltage. It achieves a 12μm×12μm pixel size, a frame rate of 72 fps, a FPN of 0.45%, and a temporal readout noise of 1.09mVrms (with 16 times of pseudo-multiple sampling), respectively.