Abstract
The applications involving high-rate LDPC codes have been widely discussed. However, it is hard for high-rate LDPC decoders to achieve high throughput, lower complexity, and fast decoding convergence speed. The convergence speed of shuffled message passing decoding (SMPD) and the layered message passing decoding (LMPD) are faster than that of standard two phase message passing (TPMP) decoding. Due to complex memory access and requirement of large storage space, the conventional shuffled MPD is not suitable for hardware implementation especially for high-rate LDPC codes. On the other hand, the LMPD decoding has been broadly used in all decoder field. In this thesis, we propose a modified shuffled MPD which can achieve a similar decoding convergence speed but with reduced complexity in memory access and storage space as compared to the conventional shuffled MPD and achieve a similar convergence speed as compared to the LMPD decoding. Finally, a suitable architecture of self-rotate structure is also provided to implement an EG-LDPC (8176,7156) decoder based on the proposed algorithm and structure.