Abstract
In this thesis, we propose a computing unit, i.e., two-stage comparator, to accelerate the decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes used in the IEEE 802.16e standards based on a previously proposed decoding architecture but with small parallelism. The decoding is implemented by sequentially decoding block codes with identical parity-check matrix Hl derived from the parity-check matrix H of the QC-LDPC code. Extrinsic values are exchanged among these block codes since the code bits of block codes are overlapped. Since the dimensions of Hl are much smaller than those of H, the complexity of interconnection can be reduced. With the proposed two-stage comparator, the number of cycles of comparison is reduced. In addition, a pipeline architecture is used to increase the decoding throughput. The proposed decoder has low area complexity but with satisfactory throughput and the scalability to support LDPC codes with various lengths.