Abstract
Due to the development of power switching devices, the voltage-fed pulse-width modulation inverters have been used popularly in industrial applications. One of the main problems encountered in open-loop PWM inverter drives is the output voltage error caused by the blanking time. Although, in PWM inverters, the dead-time is needed to prevent the short circuit of the DC bus, distorts the applied PWM signal, results in a decreased fundamental output voltage, current distortion, and motor torque ripples. If not compensated, this problem will damage the output voltage precision. To deal with this problem, various dead-time compensation schemes have be presented, but their compensation are not complete. In thesis, an integrated pulse width modulator with dead-time generator is presented. The proposed modulator can place proper dead-time around gating pulses while maintaining the correct volt-second of the output voltage on a pulse-by-pulse basis. The proposed method is suitable for digital implementation of PWM, and the required computational resource is very low. Compared to the conventional dead-time compensation by average voltage correction, the proposed method provides improved accuracy of output voltages and hence better dynamic response. Experimental results are provided to verify the proposed method. Comparisons with other dead-time generation/compensation method are also presented.