Abstract
View-interpolation-based refocusing requires a large number of novel views to generate a single refocused image. To realize real-time refocusing, novel pixels needed to be generated are dramatically high. Conventional view interpolation methods usually suffer from high computation complexity and irregular memory access, and therefore they are difficult to achieve real-time refocusing with limited hardware resources. In this thesis, we aim to design and implement a view synthesis engine for real-time realistic refocusing. Based on a center-based 1D line scan view synthesis algorithm, which is specifically designed for refocusing, we analyse the algorithm and find two design challenges for hardware implementation. The first challenge is to deal with asynchronous input access of central and right views, which makes the buffer design and the parallelism design difficult. The second challenge is to reduce a long critical path which consists of an iteration bound. The first challenge is solved by proposed multi-pixel throughput FIFO buffers. The FIFO buffers are applied for central, right and novel views respectively to make data access independent, and the multi-pixel throughput is designed to achieve parallel computation. The parallel designs of the algorithm are analysed and the best parallelism number is four, because it achieves the same output throughput with smaller hardware resources. To reduce the iteration bound, a proposed look-ahead structure and a retiming technique are used to greatly reduce the critical path. As a result, the maximum clock rate can be increased from 125 MHz to over 200 MHz. A view synthesis engine is implemented to support real-time Full HD refocusing. The required novel pixel rate is over 5 Gpixel/s. To achieve this requirement, eight 1D view synthesis engines are needed. Since so many engines consume enormous hardware resources, a precision analysis shows that we can use the less precise dividers for linear interpolation engines to greatly reduce the number of gate count with only a little distortion. Based on logic synthesis results using TSMC 40nm process, the final design consumes 687k gates, and performs 30 fps for Full HD refocusing.