Abstract
Recently, rapid development of wireless communication systems demands high performance, high speed, and low power CMOS RFICs. This study focuses on high performance VCOs and mixers for wireless communications. Because the system IIP3 is mainly dominated by the stage following low noise amplifier, we especially focus on the linearity of mixers. This thesis is divided into two parts as follows. First, low power and high performance mixer and VCO are designed and fabricated by TSMC CMOS 0.18 m process. A mixer can operate under 1V and achieve good conversion gain, fair noise figure and IIP3. The VCO is co-designed with LDO (low drop-out) regulator and bandgap. Using the cascode current reused topology, we can save considerable amount of power and obtain superior phase noise reduction and FOM. Finally, we implement a mixer by using a VCO to generate differential LO signals and adopting the proposed calibration mechanisms. We observe the dependence of the mixer performance on LO signals and investigate the relation between the VCO and the mixer. In the second part of this dissertation, we present two linearized techniques and describe two high linearity mixers implemented with these techniques, which are also designed based on TSMC CMOS 0.18 m technology. The injection block reported here can cancel the output IMD3 terms. This is also verified by mathematic derivations. This design can achieve a high IIP3 up to 15dBm and maintain the conversion gain at about 10dB, while adding the power by only 0.25mW. The second mixer’s RF stage transconductance is linearized by using two paths: one is the main conversion gain path and the other is auxiliary path. The RF current’s nonlinear term is cancelled by the auxiliary path, and the IIP3 is significantly enhanced to 17dBm, an additional power of 10mW is needed to maintain an 8dB conversion gain.