Analysis of Sub-5 nm Transistors Trend by 3D TCAD Simulation

Thesis

Du, Yan-Ting

Masters, 國立清華大學, 工程與系統科學系

2017

Abstract

次五奈米

矽鍺通道

退後井製程

環繞式閘極

奈米薄片

無接面式電晶體

Sub-5 nm

SiGe channel

Super Steep Retrograde Well

Gate-all-around

Nanosheet

Junctionless FET

abstract hide

1 Record Views

Title: Analysis of Sub-5 nm Transistors Trend by 3D TCAD Simulation
Translated title: Analysis of Sub-5 nm Transistors Trend by 3D TCAD Simulation
Creators: Du, Yan-Ting
Contributors: Wu, Yung-Chun (Advisor)
Lin, Yu-Hsien (Advisor)
Awarding Institution: 國立清華大學, 工程與系統科學系; Masters
Theses and Dissertations: Masters, 國立清華大學, 工程與系統科學系
Language: English
Resource Type: Thesis
Date published: 2018