Abstract
In the modern SoC, multiple processors are commonly integrated into the single chip. Network-On-Chip (NOC) is considered as a promising solution for on-chip inter-core communication. Owing to the rapidly increasing number of processors, verification and debugging of the inter-core communication has become one of the most important issues to be taken into consideration. As the reason, we put emphasis on the trace and debug for the inter-core communication issues. In the thesis, we proposed an application-level transaction-based trace infrastructure for NoC-based many-core platform which monitors the local bus in each processor element (PE). The proposed trace infrastructure is composed with the configurable real-time bus tracer and the proposed On-Chip Communication (OCC) Recognition Unit. The trace method in OCC Recognition Unit is based on the event-based application level trace. In order to solve the inter-core communication problem, the specific events are defined according to the data transmission protocol and the value of target registers. Thus, the monitored bus signals are traced only when the specific event occurs. Furthermore, the complex lower level hardware signals are converted to an application-level data corresponding to the occurrence of pre-define event. We also provide the off-line parser to parse the trace data to restore the progress of transmission and provide the direct information to the software programmer. In addition, the debugging flow is proposed which can be adopted in different level of many-core systems to debug the inter-PE communication problem efficiently with the aid of proposed trace infrastructure. In our work, the SystemC platform is adopted to do cross-verification and to analyze the behavior of the On-chip Recognition Unit. It can raise the cycle-based level to higher transaction-based level, so it provides faster simulation speed. With the data size comparison experiment, the size of traced data with application level trace can be significant reduced by 99.6% as compared with the transaction level trace and 99.7% as compared with the signal level trace. For demonstrating the capability of debugging and diagnosing, we adopted two typical user cases to introduce the FIFO full issue and cache miss coherency issue which are important common issues on many-core platform that may cause the inter-PE communication failure.