Abstract
As the number of cores in a chip increases continuously, Network-on-Chip (NoC) becomes the primary choice for interconnecting the cores. Exploring the design of NoC is hence important. To study a new NoC architecture, architects tend to establish an early-stage model of the interested architecture for evaluation and exploitation of the design space. The results are then used to guide the detailed implementation of the architecture. For fast evaluation and exploitation, trace-driven simulations are often preferred. The problem is that traces require huge space to store and are difficult to transport over the network. By observing that traces usually contain many repetitive, redundant communication patterns, a pattern-driven and interval-based traffic generator, Attackboard, was recently proposed. The idea is to build a small table of communication patterns that can be used to generate traffic to NoC on-the-fly during simulation, whereas the traffic is similar to that generated by the original trace. However, Attackboard requires well-tuned design parameters to obtain an acceptable accuracy compared with the original traces. This therefore limits the applicability of Attackboard. In this thesis, we propose Attackboard Plus, which uses a new two-level dependency-aware table to generate NoC traffic. It improves Attackboard by eliminating those design parameters and better matching the communication patterns in the original trace. Our evaluations show that Attackboard Plus achieves higher accuracy with slightly higher storage space overhead compared with Attackboard. Case studies on NoC design space exploration show the applicability of Attackboard Plus in general, though some limitations need to be observed.