Abstract
In order to scale CMOS field-effect transistors (FETs) well into the sub-20-nm regime, multi-gate structures, such as FinFETs, double-gate, and surround-gate structures, have become the mainstream technology. However, the three dimensional structure and the raised source/drain with expanded volume that is usually used in FinFET technologies can lead to increased parasitic capacitance effects. The serious parasitic effects affect the device performance and limit the further scaling of CMOS technology. The extraction of parasitic capacitance in FinFET is critical to analyzing circuit performances. In the past few decades, several extraction methodologies for characterizing the parasitic resistance of a transistor have been developed. Most of these methods have difficulties in reaching resolution levels below femtofarad, and requires test patterns that consist of large arrays of parallel connected transistors. The added wiring and corresponding fringing capacitance in these transistor arrays can lead to significant sources of error. A novel approach for the parasitic capacitance extraction of nanoscale FinFETs using specially designed CMOS-process-compatible floating-gate devices is proposed in this work. The new method requires no enlarged test patterns, nor additional measurement circuits and enables the extraction of extremely small parasitic capacitance of FinFET devices. By obtaining the channel current measured from the control gate, different capacitance components can be extracted. This novel scheme is demonstrated using CMOS process compatible in the characterization of parasitic capacitance with atto-farad resolution. Three-dimensional simulations are presented to compare the new scheme with the conventional current charging method. The capacitance and resistance in FinFET devices are also analyzed using simulations.