Abstract
With rapid growth and evolution of multimedia applications, the demanded computation has been putting more and more pressure on processing capability of modern processors. Aiming at high performance and relatively low cost, a majority of embedded systems have adopted Digital Signal Processors (DSP) as their optimum solution. For achievement of higher computing ability, DSP has been equipped with many hardware optimizations specific to multimedia applications. One developing trend in DSP is to augment DSP instruction sets with short vector instructions, called sub-word instructions. Sub-word instructions operate sets of data in a Single Instruction, Multiple Data (SIMD) manner. Tremendous benefit of multimedia processing is provided since sub-word instructions accelerate processing for adjacent data with short data types. However, access to these sub-word instructions is, unfortunately, limited to in-line assembly, library, and compiler intrinsic functions, but not applicable for general C language constructs for efficiency support. In order to take advantage of sub-word instructions both for old and new programs, auto-vectorization was consequently proposed to generate sub-word instructions automatically in compilers. The goal of auto-vectorization is to exploit parallelism implicit in user programs and leverage sub-word instructions in code generation. With auto-vectorization, efforts of parallel programming and legacy program rewriting are largely saved. Moreover, performance of multimedia applications could be boosted for several times according to the data types used. In this thesis, we present an enabled flow for performing auto-vectorization of C compilers by utilizing sub-word instructions. The vectorizing compiler would identify data level parallel implicit in C programs and automatically generate assembly with sub-word instructions whenever possible. The target architecture in our experiment is based on PAC VLIW DSP processors. The performance of vectorized programs are evaluated using a set of DSP loop kernels, which are typical and representative in digital signal processing. The preliminary results reveal that our vectorizing compiler generates codes with efficiency. The speedup is from 1.3 to 2.1 compared to the one without our proposed optimizations.