Automatic DLL-Based Clock Synchronization Scheme for Multi-Die ICs

Thesis

Cheng, Chia-Yuan

Masters, 國立清華大學, 電機工程學系所

2017

Abstract

時脈訊號偏差量

時脈訊號同步

鎖延遲迴路

多裸晶晶片

鎖延遲迴路編譯軟體

Clock Skew

Clock Synchronization

Delay-Locked Loop

Multi-Die IC

DLL Compiler

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Title: Automatic DLL-Based Clock Synchronization Scheme for Multi-Die ICs
Translated title: Automatic DLL-Based Clock Synchronization Scheme for Multi-Die ICs
Creators: Cheng, Chia-Yuan
Contributors: Huang, Shi-Yu (Advisor)
Awarding Institution: 國立清華大學, 電機工程學系所; Masters
Theses and Dissertations: Masters, 國立清華大學, 電機工程學系所
Language: English
Resource Type: Thesis
Date published: 2018