Abstract
In the event of unreliable test data communication, e.g. the wireless test system, packets with error correction and resent capability are preferred to encapsulate information. Yet, it is difficult for circuit/test designers to construct such test interface (or test wrapper) for this purpose. Also, it is inefficient to use hard Intellectual Properties (IPs) in this case, since every device under test (DUT) have different requirements. One solution is to synthesize the wrapper automatically based in a description capable of characterizing the functionality of a DUT. In this thesis, we will use the IEEE standard (IEEE 1450.6) a.k.a. Core Test Language (CTL) to describe the test targets, and propose a synthesis tool to create wrappers for the target DUTs. In the meantime, the test program run on testers can be generated automatically. The architectures of wrappers are modular to support different ATE platforms (other than wireless channels), and they can be used in multiple clock domains as well. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. The automation concept has been realized in this work. For demonstration purpose, we employed a wireless test system as the target test platform. In such system, a test wrapper serves as a bridge between communication modules and DFT circuits. In the experiments, we have demonstrated that the proposed tool can synthesize the test wrapper as well as the test program automatically for heterogeneous DUTs. As shown in experimental results, the area of synthesized test wrappers are under 5.1k gates for the test cases with area overhead lower than 4.31%. Moreover, an integrated chip has been tapped out which includes DUTs (memories), BIST, test wrappers and communication modules (analog parts included).