Abstract
錯誤更正碼是用來保謢數位資料在傳輸的過程免於錯誤的發生。BCH 碼則是一種對於錯誤獨立發生時，能夠更正錯誤的最佳結構化的碼。 傳 統 BCH 碼解碼器只能在設計距離內更正錯誤，而不能在真正距離內更正 錯誤，這會限制到解碼器錯誤更正的效果；因此，完全利用到錯誤更正碼 特性的最大可能式解碼器就可解決上述的問題。 在本論文中，我們提 出一個新型管線式的架構來達到 BCH 碼最大可能式的硬 ( 軟 )式解碼。 所提出的架構是根據陪集解碼的解碼法則，在這個法則中，每個子集的解 碼過程採用向量量化器的架構來實現，由於此架構是一心脈式架構，所以 擁有規則性、模組性的特點，因此非常適合以超大型積體電路的方式實現 。 我們利用 0.6 微米的 CMOS 製程技術來設計二元 BCH (21, 12, 5) 碼的硬式解碼器原型， 整個電路佈局大小約為 9.48 毫米 ( 高 ) * 8.94 毫米 ( 寬 )， 其解碼速度可達 125MHZ，若增加一點額外的面積， 所設計的解碼器可達 875MHZ 的解碼速度。 另外，所提出的架構可應用 到 Golay (24, 12)碼的最大可能式軟式解碼，跟之前被提出的解碼器比 較，所提出的架構具有較高的解碼速度且較容易以超大型積體電路的技術 實現。 Error correcting codes are used to protect digital data against errorswhich occur during the transmission through a communication channel. The Bose-Chaudhure-Hocquenghem (BCH) codes have proven to be the best constructivecodes for channels where errors affect consecutive symbols independently. Theconventional algebraic decoding process for the BCH codes can only decode thereceived vector within the designed distance, instead of the actual minimumdistance; this would somewhat limit the performance of th e decoder. Incontrast, the maximum-likelihood (ML) decoding process makes full use of thecode characteristics and channel information, and can reach betterperformance. In this thesis, we propose a new pipelined architecture for ML hard/softdecision decoding of the binary BCH codes. The proposed architecture is basedon coset decoding, where several sub-decoding processes are involved and eachone is realized by vector quantization techniques. It possesses the featuresof regularity and modularity, and is thus suitable for VLSI implementation. Aprototype chip of the proposed decoding architecture has been designed for thebinary BCH (21, 12, 5) code. Simulation results s how that the decoder canprovide a throughput up to 125 Mbit/s under 0.6um CMOS VLSI technology. Thechip area required is about 9.48 * 8.94 mm^2. With a little more area penalty,the throughput of the designed ML decoder can be increased to 875 Mbit/s. Theproposed architecture can also be applied to the ML soft-decision decoder forthe Golay (24, 12) code. As compared to the previous hardware ML decoder, theproposed one has a much higher decoding rate and is more easily realized.