Abstract
As users implement more circuits operating at high speed in FPGA and more defects affect the delays with the advances of VLSI technology, FPGA delay-fault testing is becoming more important. The current delay-fault testing for FPGA is practiced by configuring the FPGA with different designs and running them at speed. It can't guarantee the performance of users' circuits since it is impossible to configure the FPGA with all possible designs. Given the low overheads of implementing FPGA BIST and high cost of at-speed ATE, BIST for delay faults in FPGA is the preferred platform. In this thesis, we proposed a new BIST-based approach for FPGA interconnect delay faults. It can operate at rated clock speed and test most components on interconnects without being affected by clock skew. Thus, it has high delay fault detectability to test the faulty interconnects. Besides, it can be applied to FPGA manufacturing test because it can be independent of the end application. We will use Xilinx Spartan series FPGA to demonstrate the BIST structure, and evaluate our method by an efficient FPGA fault simulator. In our experiment, the fault coverage can be more than 98\% even under influence of multiple delay defects. The total number of required test configurations is 36 and independent of array size. Additionally, the overall test time is approximately 6.46 seconds.