Abstract
Interposer-based 2.5D-IC and fan-out wafer level packaging (FO-WLP) technologies are becoming attractive and viable multi-die integration solutions for designs that require lower power and heterogeneous components. However, to make a highly integrated multi-die IC reliable, various design issues remain to be solved. In addition, for a bus-rich multi-die IC, how to plan inter-die bus connections is also an important and challenging design task. In this thesis, we propose several methods for bus-rich designs each of which consists of multiple dies integrated on a platform that could be a silicon interposer or FO-WLP. These methods include how to place a set of dies on the platform, how to assign signals to TSVs (for the interposer case) or solder balls (for the FO-WLP case), and how to iteratively refine the placement and signal assignment results. The experimental results show that the proposed methods are friendly to bus-rich designs, the refinement process is effective, and the speedup is significant when the proposed acceleration techniques are used.