Abstract
As the device geometry continues to scale to deep sub-micron, high dose implant is essential in the source/drain for device optimization. However, in photoresist strip step of high dose implant process, carbonized photoresist residue becomes a critical issue. To effectively and completely remove any residue photoresist, a fluorine-based gas such as CF4 was widely used in photoresist ashing applications. A non-optimized CF4 ashing recipe would cause fluorine penetration into the gate oxide and affect device characteristics. In this work, different CF4 plasma process times were used in the source/drain photoresist strip process and the fluorine atoms were introduced into the polysilicon gate. The experimental result showed that longer CF4 plasma process time gave rise to additional gate oxide thickness and higher threshold voltage. Negative shift of flatband voltage were also found due to positive oxide trapping charge by CF4 plasma. A robust Si-F bond at the interface of SiO2/Si formed by CF4 plasma instead of original Si-H bond led to good immunity to hot carrier injection (HCI) stress and improved negative bias threshold instability (NBTI). But lower voltage-to-breakdown (Vbd) and charge-to-breakdown (Qbd) were also observed. This gate oxide integrity (GOI) degradation was triggered by the CF4 plasma-induced oxide trapped defects and happened especially in finger-type poly-Si gate test pattern which provided more exposed grain boundary for fluorine penetration than bulk–type one.