Abstract
In write-invalidate snoop based cache coherence protocol, write operations that affect coherence are broadcasted to invalidate data in other caches. In general, cache invalidation interferes normal cache operation and has performance impact because each invalidation need to perform cache address lookup. However, a lot of invalidation messages snooped by the cache are redundant. In this paper, we classify the redundant cache invalidation messages and propose a novel architecture that can eliminate the interference of all categories of redundant invalidation messages to the cache. Conceptually, we use a table to store the incoming invalidation messages. To realize this table, nevertheless, we have to resolve the limit-capacity issue. In this paper, we also propose a methodology for deleting those outdated invalidation messages and resolving the size limitation of the table. Our results show that on average, our approach achieves 8.0% faster than MESI protocol running on four processors, and 30.01% faster than MESI on eight processors.