Abstract
With the demand of shorter production period today, High-level-synthesis (HLS) and the electronic-system-level (ESL) technology become more important recently. In our previous work, we proposed a communication unit for controlling the packet send and receive on the Network-on-Chip (NOC). Because we have both the RTL and ESL version of this design. We choose this design and implement to HLS version in di erent method and compare the result with manual RTL design. We implement a HLS design base on the manual RTL, which is completely compatible with the original RTL design after HLS. And then we implement a behavior based HLS design. We implement this design based on the behavior from ESL design and use a syn- thesizable interface. We can synthesis the interface to AXI3 with simple bus library. We both interesting in the micro-architecture setting. The S2Cbench is an open source and synthesizable SystemC testbench, we choice this testbench to synthesis with di erent micro- architecture and compare the result. From the analyzing of the di erent micro architecture result, we nd some special case when certain micro architecture setting. And nding the reason to explain the special case by observation the information from HLS tool.