Abstract
This thesis proposes a cell-based Time-to-Digital Converter (TDC) architecture and its compiler, which can generate cell-based TDC circuits automatically. Because the values from data book are approximations and the result could vary from different routing conditions in APR stage, the quantized outcome of shrinking line may not meet the expectations. In order to solve this problem, the resolution of fine-shrinking cells are pre-confirmed in transistor level simulation. It also reorganizes the components that are suitable for pulse-shrinking architecture in TSMC 90nm CMOS process technology. A coarse block with an adjustable shrinking amount is used to prevent the side effects of the process variation. The output digital code is turned into an absolute value by a built-in interpolation scheme to make the back-end operation intuitively. The error caused by clock jitter during the interpolation is reduced by a multi-sample methodology. The proposed system can generate a TDC circuit in minutes with user’s specification. It saves not only time but effort in the design flow. The result from simulation shows that the proposed TDC compiler can support input range from 1ns to 8ns with many choosable shrinking cells and different target ranges. These features increase the flexibility of TDC compiler greatly.