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Cell寬頻引擎的管線化H.264解碼器製作
Thesis

Cell寬頻引擎的管線化H.264解碼器製作

Wu, Liang-Fu
Masters, 國立清華大學, 資訊工程學系
2009

Abstract

H.264 Cell寬頻引擎 平行化 多核心 SIMD 直接內存訪問 H.264 Cell Broadband Engine Parallel Multicore SIMD Doctor of Musical Arts (DMA)
With the growing number of applications involved with video compression and decompression, video CODEC like H.264 plays an important role in modern market. H.264 achieves the highest compression efficiency targeting at the requirement of High Definition (HD) video contents at present, but the cost is the demand of high computational complexity. As a result the processor must be advanced to attain good performance for H.264. However, due to the well-known energy consumption and heat radiation issues, multicore platform becomes the main trend in computer architecture. In order to approach peak performance, multi-core platform’s characteristics must be taken into consideration. Also when parallelizing the H.264 algorithm, the CODEC must be exploited and evaluated to solve the complex dependencies in it. One of the popular multicore platforms is the IBM Cell Broadband Engine (Cell B.E.), which is a heterogeneous chip multicore processor composed of one Power Processor Element (PPE) and eight Synergistic Processor Elements (SPEs). The Cell BE is specially designed to meet the high performance requirement for multimedia applications with Single Instruction Multiple Data (SIMD) and Direct Memory Access (DMA) units inside. It also provides a rich set of libraries and APIs for application development. With the strength of Cell BE, we should be able to reduce the burden of computation introduced by H.264. In this thesis, the data parallelism and task parallelism are exploited to bring up a combinational parallel decoder based on JM’s open source H.264 decoder. PPE distributes two slices at a time, with two pipelined decoding flow each being composed of 4 SPEs. Double buffering is employed to process the slices independently. The theoretical speedup is 9 times comparing to sequential execution on PPE. Deblocking module is offloaded to SPE with double buffering used in the experiment, and the speedup is 1.17 times.

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