Abstract
Orthogonal frequency division multiplex access (OFDMA) is employed in the next-generation mobile communication systems. In OFDMA system, subcarriers can be grouped as several resource blocks and allocated to different users. So partial subcarriers of one OFDM symbol are used by one user and full FFT computation is unnecessary for low-power requirement. If we can only compute the required part of full FFT computation in terms of allocated resource blocks, the power consumption and processing time can be saved efficiently. In this thesis, we propose a partial cached-FFT algorithm on cached-memory architecture to control the operation of cached-FFT architecture in terms of allocated resource blocks. By proposed partial cached-FFT algorithm, we design a variable-length partial cached-FFT processor from 128-point to 1024-point. In addition, twiddle factor multiplier is computationally intensive element of one butterfly operation. So the power-aware multiplier is designed in terms of signal dynamic range in FFT computation and different constellation in order to reduce power consumption. Finally, we use the cell-based design flow to implement proposed design with TSMC 0.18um cell library. By the proposed processor, we can reduce power consumption to 36.34% of full FFT computation at most.