Abstract
Compared with the amorphous-Si thin film transistors (TFTs), low-temperature poly-Si (LTPS) TFTs have higher mobility that help shrinking the transistor dimension, enhance the circuit operation speed, increase the transistor density on circuit, and add function of design capability of the circuit. The Pi-gate nanowires (NWs) with TaN metal gate and Al2O3 blocking layer were introduced to the poly-Si TFT nonvolatile memory. These devices have drawn much attention because of their wide applications on active matrix crystal displays (AMLCDs), and organic light emitting diodes (OLEDs). Furthermore, the LTPS TFTs will help to carry out three-dimensional integrated circuits (3D-ICs) for system-on–chip (SOC) and fully functional system-on-panel (SOP) applications. In this thesis, introducing NWs channel in NVM increase gate controllability and program/erase speed (P/E) speed. The P/E speed and data retention can be improved by introducing Al2O3 high-κ blocking oxide. The erase efficiency of the TaN gate device is higher than the Poly-Si device due to the work function of the TaN is higher than the Poly-Si. The unwanted backward FN tunneling current of electron through the blocking oxide is significantly suppressed. Because of the discrete traps of Si3N4, two-bit operation could be achieved. We discuss two kinds of two-bit operations. In addition, we discuss the dual gate poly-Si TFT NVM with Al2O3 blocking layer and TaN metal gate. Dual gate devices exhibit low leakage current in the off state and high program and erase speed due to the more edge-induced fringe electric field at each corner. A novel two-bit per cell operation is performed by modulated Fowler-Nordheim (MFN) programming and band-to-band tunneling-induced hot-hole injection (BTBT HH) erasing. The dual gate TANOS memory shows larger memory window and clear distinguish ability than single gate memory under two-bit operation