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Characterization of CMOS-micromachined,Two-dimensional Transistor Arrays for Bidirectional Neural-electronic Interface
Thesis

Characterization of CMOS-micromachined,Two-dimensional Transistor Arrays for Bidirectional Neural-electronic Interface

Chin-Hsiang Chang
Masters, 國立清華大學, 電子工程研究所
2007

Abstract

神經-電子介面 氧半電晶體 CMOS製程相容 神經訊號紀錄、刺激 單晶片系統 生醫感測器
The field of neuroscience has drawn gradually expanding attention ever since the middle of 20th century. This is generally because the desire of human beings to understand ourselves and that people start to realize certain things are accomplished more efficiently in the biological world than it is being done today. Many scholars dedicate their study into bio-inspired, or more specifically, brain-inspired research to further improve our living environments. Among all existing apparatuses available for monitoring the response of neuralnetworks, MicroElectrode Array (MEA) gains the most conspicuous attention because it allows researchers to communicate with a great quantity of biological signal processing units (also known as neuron) simultaneously in a harmless way. In this thesis, we try to identify a MEA system which is fully compatible with current VLSI technology. Under the consideration of sensitivity, signal integrity and system scalability, a CMOS-compatible OSFET based MEA chip with integrated circuitry was developed, where OSFET is simply a MOSFET without its poly gate. This thesis will first give a quick review in the fabrication method of the prototype MEA chip. After that comes the complete exams of the 1st generation chip, from electrical tests (process variation, sensory drift, noise measurement, circuit performance) to biological tests to verify its functionality. Experimental results confirm the validity of both recording and stimulating neurons using the chip while several imperfections have been found during the testing. Based on these collected information, the characters of using such sensors in monitoring neural activities and its proper back-end circuit topology will then be concluded. These feedbacks will be discussed in the end of each chapters and finally, an modified 2nd version OSFET MEA chip is designed and taped out to overcome existing problems.

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